A phase-locked loop (PLL) circuit includes a charge pump that performs a charge and discharge operations for a loop filter in accordance with phase difference information. A charge pump circuit that is used for a voltage controlled oscillator (VCO) in order to increase a range of control voltage of the VCO of the PLL circuit includes a current mirror configuration by which charge current and discharge current become equal.
Related arts has been discussed in Japanese Laid-open Patent Publication No. 6-61859, Japanese Laid-open Patent Publication No. 2000-114891, a paper entitled “A Fully On-Chip 10 Gb/s CDR in a Standard 0.18 um CMOS Technology” Jinghua Li, et al., IEEE Radio Frequency Integrated Circuits Symposium, 2007 No. 9, P. 237-240, or a paper entitled “SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application” Yuriy M. Gireshishchev, J. Solid State Circuits Vol. 35, No. 9, P. 1353.